The present disclosure relates generally to information handling systems (IHSs), and more particularly to memory module optimization for an IHS.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
IHSs include memory modules that store data which is used during operations of the IHS. A type of memory module includes dynamic random access memory (DRAM) circuits which are known as dual in-line memory modules (DIMMs). These memory modules are generally removable from the IHS using one or more memory sockets so that a user can add, remove, or replace memory modules.
DIMMs may operate using a standard known as a double-data-rate (DDR) standard. There are also mutually exclusive DDR standards known as DDR2, DDR3 and DDR4. An IHS may have two or more memory sockets, and each socket may couple with a different type of DIMM using a different standard (e.g., DDR2 or DDR3). In other words, there a number of different DIMM types that may be installed into an IHS via an industry standard connector socket. One such socket is known as a 240-pin DDR3 connector. IHSs generally support different DIMM types, such as unbuffered DIMMs (UDIMMs), registered DIMM (RDIMMs), and load reduced (aka “Load Decoupled” or “High-Density Reduced Load”) DIMMs (LR-DIMMs). However, different types of DIMMs consume varying numbers of clock signals (CLK), clock enable signals (CKE), on-die termination signals (ODT), and rank chip select signals (CS). Some of these signals are configurable via LR-DIMM control and status registers (CSRs). Complicating memory configuration matters for IHS designers, the number of physical ranks per DIMM varies from 1 to 8, the number of different operating voltages is 2 and will soon be 3, and the number of possible operating frequencies is now 3 but will soon be 5-6. An operating frequency of a DIMM is a function of DIMM type, number of data and address/control loads per DIMM, IO drivers, and physical channel characteristics.
Additionally, memory controllers that control the DIMMs have a limited number of clock signals, clock enable signals, on-die termination, and rank chip select signals available per channel due to either physical ball-out and package limitations, memory controller CSRs and logic limitations, or other limitations. Thus, the controllers typically provide a generally useful set of control signals for many, typical applications, and provide the system provider some flexibility as to how to hook them up to actual DIMM sockets. However a design issue exists for current DDR2 based servers, such as those using Advanced Micro Designs (AMDs) socket F processors, which support only RDIMMs. Due to memory controller chip select limitations (e.g., 8 per channel), the system provider needs to determine if they support 2 DIMMs per channel with 4 chip selects per DIMM (e.g., up to quad rank), or if they support 4 DIMMs per channel with only 2 chip selects per DIMM (e.g., up to dual rank). This selection is limiting to the IHS designer and is done via point-to-point routing of chip selects to DIMM connectors.
Accordingly, it would be desirable to provide a system for IHS memory module optimization.